NCP1651DR2G【PDF 18/32 页】IC PFC CONTROLLER CCM/DCM 16SOIC

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Sheet目录45

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NCP1651

http://onsemi.com

OPERATING DESCRIPTION

DC Reference and Buffer

The internal DC reference is a precision bandgap design

with a nominal output voltage of 4.0 volts.It istemperature

compensated, and trimmed for a g1% tolerance of its

nominal voltage, with an overall tolerance of g2%. To

assuremaximumstability,thisisonlyusedasareferenceso

there is minimal loading on this source.

TheDCreferenceisfedintoabuffer with again of 1.625

which creates a 6.5 volt supply. This is used as an internal

voltagetopowermanyoftheblocksinsideoftheNCP1651

andisalsoavailablefor externaluse.The6.5volt

reference

is designed to be terminated with at 0.1

F capacitor

for

stability reasons.

There is no buffer between the internal and external

6.5 volt supply, so care should be used when connecting

external loads. A short or overload on this voltage output

will inhibit the operation of the chip.

Undervoltage Lockout

An Undervoltage Lockout circuit (UVLO) is provided to

assure that the unit doesnot exhibit undesirable behavior at

lowV

levels.Italsoreducespowerconsumptiontoalevel

that allows rapid charging of the V

cap.

When the V

cap is initially charging, the UVLO will

holdtheunitoff,andinalowbiascurrentmodeuntiltheV

voltage reaches a nominal 10.8 volt level. At this point the

unit will begin operation, and the UVLO will no longer be

active. If the V

voltage falls to a level that is 1.0 volts

below the turn- -on point, the UVLO circuit will again

become active.

When in the active (shutdown) state, the UVLO circuit

removespowerfromallinternalcircuitrybyshuttingoffthe

6.5 volt supply. The 4.0 volt reference remains active, and

the UVLO and Shutdown comparators are also active.

Multiplier

The NCP1651 uses a new proprietary concept for its

Referencemultiplier.Thisinnovativedesignallowsgreatly

improved accuracy compared to a conventional linear

analog multiplier. The multiplier uses a PWM switching

circuit to create a scalable output signal, with a very well

defined gain.

One input (A) to the multiplier is a voltage- -to- -current

(V- -I) converter. By converting the input voltage into a

current, an overall multiplier gain can be accomplished. In

addition,therewillbenoerrorintheoutputsignalduetothe

series rectifier.

The other signal (Input P) is input into the PWM

comparator. This selects a pulse width for the comparator

output.ThecurrentsignalfromtheV- -Iconverterisfactored

bythedutycycleof thePWMcomparator,andthenfiltered

bytheRCnetworkontheoutput.Thisnetworkcreatesalow

passfilter,andremovesthehighfrequencycontentfromthe

original waveform.

Figure 32. Simplified Multiplier Schematic

FB/SD

INPUT P

RAMP

OUTPUT

Inverting Input

V to I

CONVERTER

Themultiplierrampisgeneratedbytheinternaloscillator,

andisthesamesignalasisusedinthePWM.Itwilltherefore

have the same frequency as the power stage.

ItisnotnecessaryforInputP(intothePWMcomparator)

tobeaDCsignal,lowfrequencyACsignals(relativetothe

ramp frequency) work well also.

The gain of the multiplier is determined by the

current- -to- -voltage ratio of the V- -I converter, the load

resistoroftheoutputfilterandthepeakandvalleypointsof

thesawtoothramp.WhenthePinputsignalisatthepeakof

the ramp waveform, the comparator will allow the A input

signaltopasswithoutchoppingitatall.Thisgivesanoutput

voltage of the A current multiplied by the output filter

resistance. When the P input signal is at the ramp valley

voltage,thecomparatorisheldlowandnocurrentispassed

intotheoutputfilter.Inbetweenthesetwoextremes,theduty

cycle(andtherefore,theoutputsignal)isproportionaltothe

level of the P input signal.

TheoutputfilterisaparallelRCnetwork.Thepoleforthis

network needs to be greater than twice the highest line

frequency (120 Hz for a 60 Hz line), and less than the

switching frequency. A recommended starting point is a

factor of 20 to 50 less than the switching frequency.

The pole is calculated by the formula:

2 ???R ?C

So, for a 60 Hz line, and a 100 kHz switching frequency,

a2.0 kHzpoleisagoodstartingpoint.Thiswouldbeafactor

of 50 below the switching frequency, and is still far enough

abovethe120 Hzrectifiedlinefrequencythatitwontcause

undesirable distortion.

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